Portoscope Part 2: Hardware
Analogue circuit Yep let’s start with the toughest bit. To begin with I am not very good with analogue circuit design and the problem with this project is that it requires perfect analogue design. The output should be noise-free, not distorted and should not have any offsets.
=== Figure 2: DSO’s input circuit So to design this circuit I had to do lots of digging on Google and I found a nice book by Ian Hickman called Digital Storage Oscilloscopes, also DPScope was a helpful example. The signal starts off by getting attenuated by the frequency compensated voltage divider. The attenuation ratio I chose for this DSO was 1:10 (100Ω : 1MΩ), this allowed an input range of 0-33V. The lower limit of 0V is due to the fact that the op-amps in the circuit are powered from a single positive supply i.e. no negative supply. Op-amps are principally dual supply devices and lack of negative supply means that the output cannot swing below 0V. Upper limit is again due to the op-amps as I have used a 3.3V power rail for all ICs on the board “3.3V is the new 5V”. This means that voltages above 3.3V will be clipped by the op-amp hence 3.3V×10=33V.
Now obviously most real life signals swing below the ground level and it is important that op-amp does not clip the negative signals. To make this possible a circuit technique known as virtual ground  is used. A positive bias voltage is applied to the op-amp, generally half of the supply voltage i.e. Vcc/2. What this does is adds a DC offset (Vcc/2) to the signal or moves the signal to the positive side by Vcc/2 and makes Vcc/2 is the new ground level, virtual ground level. To control this ground level I use the analogue voltage from micro-controller’s (STM32f103VE) DAC. Default value of ground is half of the reference voltage but user has control over the ground position. DAC_SetChannel2Data(DAC_Align_12b_R, x); Variable capacitors C13 and C14 in Figure 2 are used to compensate the stray capacitance in the op-amp circuit. The balance equation for C13 capacitor is : R2||R18×C13=R3×(C11+C_par ); Where C_par is the stray capacitance Once attenuated, the signal is sent to the buffer amplifier. It does not change anything in the signal but offers very high input impedance and low output impedance, which is necessary for the vertical amplifier. Creating a buffer amplifier requires you to tie the output of an op-amp to the inverting input and signal goes into the non-inverting input. The output from buffer amplifier reaches the vertical amplifier which applies selectable gain to the signal. Here’s where things get complicated you need a variable gain amplifier and they are not very easy to design. Easy way out would be use a Programmable Gain Amplifier (PGA), they are a bit expensive and almost all of the PGAs I checked had ridiculous slew rates (<20V/us). They do reduce the design complexity and makes life easier but who wants an easy life, right? So I decided to make my own variable gain amplifier. I took a rail-to-rail op-amp (I will come back to these later) and configured it to positive feedback (output to non-inverting input). The beauty of voltage feedback op-amps is that the closed loop gain depends on the feedback resistor. Ideas? Ok use an analog multiplexer to provide different resistance feedback paths to the op-amp this way you can select feedback resistance and hence the gain.
Figure 4: Positive feedback amplifier gain So far so good! Going analogue to digital Digitizers (ADCs) are of various types and element14’s search engine has been very helpful in selecting the best ADC. Things you should look for is high sampling rate; high resolution (>8 bit) although higher than 12-bit is just pointless; high SNR (Signal-to-noise ratio) which is the noisiness of the ADC; another representation of SNR is ENOB (Effective Number of Bits) which is the noise-free bits; and Analog Devices, yes they are the authority in analog ICs. So I decided to go for AD9218 from Analog devices. It is a dual channel ADC 10-bit resolution, 40MSPS, 9.6 ENOB, which works out fine as I am using only the 9 MSBs. It has two 10-bit outputs for each channel and requires external sampling clock.
Figure 5: Acquisition circuit
Storing the digital samples from the ADC was challenging as MCUs (mine at least) are not made to access the GPIOs at that speed (40MHz). An external memory was required which could buffer the samples and later send them to the MCU. A good idea is to use FIFO memory as it works like queue and does not require addressing. I used IDT7204 FIFO which can store 2048 9-bit words and the read/write speed can be up to 66MHz.
Figure 6: Dual channel acquisition So here’s how the acquisition system works, ADCs outputs binary code word at the positive edge of sampling clock. The same clock is fed to a fast switching 12 channel digital multiplexer’s select signal, logic 0 corresponding to select channel 1 and logic 1 corresponding to channel 2. These samples are then written onto a FIFO at the negative edge of a write strobe signal, the frequency of this signal is twice the sampling rate. What the FIFO sees is alternating channel 1, channel2 samples and records them in the same manner. The FIFO indicates full state using a flag (Full flag), well the MCU sees that flag and disables the sampling process. It then reads from the FIFO by using a GPIO as read strobe signal. Similarly when the FIFO is read completely it indicates empty state flag (empty flag) the MCU sees this stops the reading and starts the sampling process again.
Figure 7: Acquisition circuit timing diagram